//************************************************
//  Filename      : singal.v                             
//  Author        : Kingstacker                  
//  Company       : School                       
//  Email         : kingstacker_work@163.com     
//  Device        : Altera cyclone4 ep4ce6f17c8  
//  Description   :                              
//************************************************
module  signal (
    //input;
    input    wire    clk,
    input    wire    rst_n,
    //output;
    output   wire [15:0]    q
);
wire [8:0] address;
reg  [8:0] cnt;
always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        cnt <= 9'd0;
    end //if
    else begin
        cnt <= (cnt == 9'd399) ? 9'd0 : cnt + 1'b1;    
    end //else
end //always
assign address = cnt;
rom_1  rom_1_u1(
    .address            (address),
    .clock              (clk),
    .q                  (q)
);

endmodule